The present invention relates to power semiconductor devices, in particular, vertical MOSFETS having MOS type gates, which use silicon carbide as a semiconductor material, and a method for manufacturing such semiconductor devices.
Silicon carbide (that will be referred to as SiC) has a wide band gap, and its maximum breakdown electric field is larger than that of silicon (that will be referred to as Si) by one order of magnitude. Thus, SiC has been considered as a material advantageously used for power semiconductor devices in the next generation. Such devices as Shottky diodes, vertical MOSFETS, and thyristors, using SiC as a semiconductor material have been proposed, and it has been confirmed that these devices exhibit far more excellent characteristics than known devices using Si. The present invention is particularly concerned with a SiC vertical MOSFET, among the above-indicated devices.
FIG. 7 is a cross sectional view of a unit cell of planar a type vertical MOSFET, which is the most prevailing type of power semiconductor device using Si. When a voltage is applied to a gate electrode layer 6 on a gate insulating film 5, a channel 10 is induced in a surface portion of a p base region 3 right under the gate electrode layer 6, and an n source region 4 and an n drift layer 2 are electrically shorted. As a result, current is allowed to flow from a drain electrode 8 formed on the rear surface of an n+ substrate 1 under the n drift layer 2, to a source electrode 7 formed on the surface of the n source region 4. When the voltage applied to the gate electrode layer 6 is removed, the drain electrode 8 and source electrode 7 are electrically disconnected from each other. Thus, the vertical MOSFET of FIG. 7 performs a switching function by applying and removing voltage to and from the gate electrode layer 6.
FIG. 9(a) through FIG. 9(f) are cross sectional views showing the flow of the process of fabricating the structure as described above. The process shown in these figures is only a part of the whole process of producing the semiconductor device, in particular, a process of forming junctions that relates to the present invention.
Initially, the n drift layer 2 having high resistance is epitaxially grown on the n+ substrate 1, and the gate insulating film 5 in the form of a silicon dioxide film (referred to as xe2x80x9cSiO2 filmxe2x80x9d) is formed by thermal oxidation on the surface of the n drift layer 2. Then, a polycrystalline silicon layer 6a is deposited on the gate insulating film 5, as shown in FIG. 9(a). The polycrystalline silicon layer 6a is then formed in a given pattern by photolithography to provide the gate electrode layer 6, as shown in FIG. 9(b).
Subsequently, p-type impurities, such as boron ions 3a, are implanted, as shown in FIG. 9(c), and the implanted boron atoms 3b are activated and diffused by heat treatment to form the p base region 3, as shown in FIG. 9(d).
Further, n-type impurities, such as phosphorous ions 4a, are implanted, as shown in FIG. 9(e), and the implanted phosphorous atoms 4b are activated and diffused by heat treatment to form the n source region 4, as shown in FIG. 9(f).
In the following steps that are not illustrated, phosphorous glass is deposited by reduced-pressure chemical vapor deposition (CVD)) to provide an insulating film, and an opening or window is formed through the insulating film, so that the source electrode 7 is formed in contact with the n source region 4. At the same time, a gate electrode is formed in contact with the gate electrode layer 6, and a drain electrode is provided on the rear surface of the n+ substrate 1.
What is most important in the above-described process is as follows: in the process of implanting the p-type boron ions 3a and n-type phosphorous ions 4a, the gate electrode layer 6 formed in the previous step serves as a mask during ion implantation, and both types of ions are introduced into the n drift layer 2 using the same mask, and then thermally diffused. The thus formed structure is called double diffusion MOS (D-MOS) structure. In this manner, the length of the channel region 10 that greatly influences characteristics of the MOSFET can be controlled with considerably high accuracy, thus assuring a high yield in the manufacture of the MOSFET.
The above-described process has been most widely employed to produce MOSFETS using Si as a semiconductor material, but cannot applied as it is when producing MOSFETS using SiC. This is because SiC has poor ability to activate impurities introduced by ion implantation, and, in order to improve this ability, ion implantation at 1000xc2x0 C. or higher and heat treatment for activation at 1600xc2x0 C. or higher are needed. In addition, the impurities introduced by ion implantation hardly diffuses in the SiC substrate.
While SiO2 film is normally used as a gate insulating film, and polycrystalline silicon is used as a gate electrode, the SiO2 film softens at 1300xc2x0 C. or higher, and polycrystalline silicon has a fusing point of 1412xc2x0 C. Accordingly, heat treatment cannot be implemented at such high temperatures as indicated above after the gate insulating film 5 and gate electrode layer 6 are formed, as in the process of FIG. 9(a) through FIG. 9(f).
In view of the above problem, trench-type MOSFET have been proposed which use SiC substrates. FIG. 10 is a cross sectional view showing a unit cell of a known example of trench-type MOSFETS.
In the structure shown in FIG. 10, a p base layer 13 is formed by epitaxial growth, rather than by diffusing impurities. Alter an n source region 14 is formed by implantation of phosphorous ions, for example, a trench 19 is formed which extends from the surface of the n source region 14 down to n drift layer 12. Gate insulating film 15 is formed on the inner wall of the trench 19, and a gate electrode layer 16 is formed to fill the interior of the trench 19. The thus formed structure may be also advantageously employed as a Si device. This is because channel regions 20 are formed in the vertical direction in this structure, thus allowing cells to be closely positioned with high area efficiency, and the resulting device exhibits improved characteristics due to its geometry.
When the above structure is employed in SiC devices, however, there arises another problem as follows. The boundary condition of the electric field strength at the interface between the semiconductor and the gate insulating film upon application of voltage is represented by:
xcex5iEi=xcex5sEsxe2x80x83xe2x80x83(1)
where xcex5i, xcex5s are dielectric constants of the gate insulating film and semiconductor, respectively, and Ei, Es are electric field strengths of the gate insulating film and semiconductor, respectively. Accordingly, the electric field of the gate insulating film is represented by the following equation:   Ei  =                    ε        ⁢                  xe2x80x83                ⁢        s                    ε        ⁢                  xe2x80x83                ⁢        i              ·    Es  
Since xcex5s of Si is 11.7 and xcex5i of the SiO2 film is 3.8, an electric field that is about 3 times as much as that of Si substrate is applied to the gate insulating film even in the case where a breakdown electric field is applied to the Si substrate. This electric field is equivalent to about 30% of the breakdown electric field of the gate insulating film. On the other hand, the xcex5s of SiC is 10.2, which is not so different from that of Si, but its breakdown electric field is larger than that of Si by about one order of magnitude, as mentioned above. In the SiC device, therefore, an electric field that is ten times as high as that in the case of the Si device is applied to the gate insulating film.
Furthermore, the trench structure as shown in FIG. 10 includes corner portions 15a. The presence of the corner portions 15a prevents the SiC device from taking advantage of its high breakdown electric field since an electric field is concentrated at this corner portion. Namely, as voltage applied to the device is increased, the gate insulating film reaches its breakdown electric field before the semiconductor reaches its breakdown electric field, thus causing the device to break down.
Recently, Shenoy, J. N. et al. has reported in 54th Device Research Conference, Santa Barbara (1996) on a prototype of SiC vertical MOSFET having a high withstand voltage. FIG. 11 is a cross sectional view showing a part of the SiC vertical MOSFET. The report states that this semiconductor device is produced by double ion implantation, though no description is provided on details of the manufacturing method. In FIG. 11, p base region 23 and n source region 24 are formed by applying increased acceleration voltage upon ion implantation so as to introduce respective impurities to large depth, thereby solving the problem of diffusion of impurities as mentioned above. This SiC vertical MOSFET is in the form of a planar structure, and is therefore free from the above-described problem of the withstand voltage of the oxide film in the trench structure.
The double ion implantation method as described above, however, has the following problem. Namely, ion implantation (or the degree of introduction of ions) varies to a great extent in different directions, whereas diffusion of impurities occurs substantially in the same way in all directions. If ions are implanted in a selected region of the substrate using a mask, therefore, the amount of impurities introduced sideways from the edge of the mask is reduced. Namely, in FIG. 11, the lateral dimension of the p base region 23, i.e., the length of the channel region 30, is reduced relative to the thickness of the region 23 in the depth direction. With the length of the channel region 30 thus reduced, punch-through is more likely to occur, and the withstand voltage cannot be increased.
To solve the above problems, the present invention provides a silicon carbide vertical MOSFET comprising: a first conductivity type silicon carbide substrate, a first conductivity type drift layer comprising silicon carbide, which is formed on the first conductivity type silicon carbide substrate; a second conductivity type base region formed in a selected region of a surface layer of the first conductivity type drift layer, a first conductivity type source region formed in a selected region of the second conductivity type base region; a gate electrode layer formed on a gate insulating film over at least a part of an exposed surface portion of the second conductivity type base region interposed between the first conductivity type source region and the first conductivity type drift layer, a source electrode formed in contact with surfaces of the first conductivity type source region and the second conductivity type base region; and a drain electrode formed on a rear surface of the silicon carbide substrate; wherein ion implantation of first conductivity type impurities for forming the first conductivity type source region is conducted using a first mask, and ion implantation of second conductivity type impurities for forming the second conductivity type base region is conducted using a second mask, the first mask having a larger width than the second mask.
In the vertical MOSFET as described above, the length of the channel region and the thickness of the second conductivity type base region can be independently controlled to desired values.
In particular, the width of the exposed surface portion of the second conductivity type base region interposed between the first conductivity type source region and the first conductivity type drift layer is preferably larger than the dimension of the second conductivity type base region as measured in a thickness direction of the first conductivity type drift layer. In this arrangement, punch-through at the channel region can be avoided, and the withstand voltage of the thus constructed MOSFET can be increased.
In one form of the vertical MOSFET of the present invention as described above, a part of at least the second conductivity type base region protrudes from a surface of the first conductivity type source region. In this arrangement, the width of the second conductivity type base region between the exposed surface portion of the first conductivity type drift layer and the first conductivity type source region can be set to a sufficiently large value.
The present invention also provides a method for manufacturing the silicon carbide vertical MOSFET as described above, wherein ions are implanted in selected regions of the first conductivity type drift layer, using different masks for forming the second conductivity type base region and first conductivity type source region, respectively, and the gate insulating film is formed after removing the masks and conducting heat treatment.
According to the above method, the gate insulating film and gate electrode layer are formed after ion implantation and activation of the implanted ions, thus making it possible to produce a planar type vertical MOSFET.
In the method of the present invention, the ion implantation of second conductivity type impurities for forming the second conductivity type base region is preferably conducted a plurality of times while varying an acceleration voltage. In this case, the thickness of the second conductivity type base region may be increased as desired.
In the above-described method, the first mask used during ion implantation of first conductivity type impurities for forming the first conductivity type source region may consist of the second mask used during ion implantation of second conductivity type impurities for forming the second conductivity type base region, and a spacer formed on side faces of the first mask. In this case, the length of the channel region can be controlled to a desired value by suitably determining the width of the spacer, and therefore the device can be easily designed with increased freedom.
The present invention also provides another method for forming a silicon carbide vertical MOSFET, which includes the steps of forming a first conductivity type drift layer comprising silicon carbide on a first conductivity type silicon carbide substrate; covering a part of the first conductivity type drift layer with a mask, and etching the first conductivity type drift layer to a given depth to form a protruding portion; implanting ions for forming a second conductivity type base region in a selected region of the first conductivity type drift layer; forming a spacer on side faces of the protruding portion formed as a result of etching of the first conductivity type drift layer; implanting ions for forming a first conductivity type source region in a selected region of the second conductivity type base region; and reducing a height of the protruding portion of the first conductivity type drift layer so as to provide a flat surface.
According to the above-described method, the protruding portion of the first conductivity type drift layer serves as a mask, and thus eliminates a need to form a thick mask made of another material that is selected to permit ion implantation of impurities at high acceleration voltage.
The present invention further provides a silicon carbide vertical MOSFET comprising: a first conductivity type silicon carbide substrate, a first conductivity type drift layer comprising silicon carbide, which is formed on the first conductivity type silicon carbide substrate; a second conductivity type base layer formed on the first conductivity type drift layer; a first conductivity type source region formed in a selected region of a surface layer of the second conductivity type base layer; a first conductivity type well region formed through the second conductivity type base layer to extend from a surface of the base layer to the first conductivity type drift layer; a gate electrode layer formed on a gate insulating film over at least a part of an exposed surface portion of the second conductivity type base layer interposed between the first conductivity type source region and the first conductivity type well region; a source electrode formed in contact with surfaces of the first conductivity type source region and the second conductivity type base layer; and a drain electrode formed on a rear surface of the silicon carbide substrate. In this arrangement, ions of second conductivity type impurities need not be implanted to form the second conductivity type base layer, and therefore the MOSFET can be more easily manufactured.
In the vertical MOSFET as described above, the first conductivity type may be n type, and the second conductivity type may be p type. In this case, the vertical MOSFET can be easily manufactured since the second conductivity type base layer is formed by epitaxial growth, without requiring ion implantation of p type impurities that are difficult to be activated.
The present invention provides a method for manufacturing the silicon carbide vertical MOSFET as described just above, which includes the steps of: forming a first conductivity type drift layer comprising silicon carbide and a second conductivity type base layer on a first conductivity type silicon carbide substrate by epitaxial growth, to provide a substrate; forming a first mask on a surface of the second conductivity type base layer, forming a second mask on the surface of the base layer such that the second mask overlaps the first mask; implanting ions for forming a first conductivity type source region in a selected region of a surface layer of the second conductivity type base layer, using the first mask and the second mask; forming a third mask on the surface of the second conductivity type base layer such that the third mask and overlaps the first mask; implanting ions for forming a first conductivity type well region in a selected region of the surface layer of the second conductivity type base layer, using the first mask and the third mask, so that the well region extends from the surface of the second conductivity type base layer to the first conductivity type drift layer through the base layer.